Friday, April 4, 2025

China unveils first indigenously designed RISC-V server processor

China unveils first indigenously designed RISC-V server processor


Chinese technology firm RiVAI Technologies has unveiled Lingyu, China's first indigenously designed high-performance RISC-V server processor. Announced at an event in Shenzhen, the Lingyu CPU is seen as an important step towards China's goal of gaining more independence in semiconductor technology.


Will be used in artificial intelligence



The Lingyu CPU adopts a single-core dual architecture approach. In addition to 32 general-purpose processing units (CPUs), there are also eight specialized smart processing units (LPUs). This structure can efficiently manage tasks such as inference for large open-source language models. The design aims to reduce the total cost of ownership (TCO) by aiming to balance processing power and energy efficiency

There is one more detail about RiVAI Technologies that has not gone unnoticed. The company was founded by Zhangxi Tan, a student of RISC-V pioneer and 2017 Turing Award winner Professor David Patterson. Professor Patterson still serves as the company's technical advisor and is promoting the proliferation of RISC-V in China.


The company has also partnered with more than 50 companies, including Lenovo and SenseTime, to support RISC-V processor adoption and ecosystem development. In this way, the company aims to move the Lingyu CPU to different platforms.

A way out for China

Unlike proprietary architectures controlled by copyright-holding Western companies, RISC-V offers an open-source instruction set. This allows Chinese companies to design and build their own processors without dependence on foreign companies. The Chinese government is also encouraging research institutions, chip manufacturers and companies to invest in RISC-V technologies. While large domestic technology companies such as Alibaba and Tencent have started to develop RISC-V-based solutions, state-funded research institutions are also working on software optimization for this architecture



 

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